Extreme level circuits have been widely used in many electrical signal processing circuits. Here, the words "extreme level circuit" are used for indicating either a maximum level circuit or a minimum level circuit. For example, such a extreme level circuit has been used in an image processing apparatus.
The Japanese Laid-open Patent P63-59596 discloses a luminance and chrominance separator for TV receivers in which such conventional maximum level circuits and minimum level circuits are used for constituting an correlation detector for determining correlations between predetermined TV signals such as line signals. Further U.S. Pat. No. 4,811,100 discloses an intermediate level circuit comprising such conventional maximum level circuits and minimum level circuits.
FIGS. 1 and 2 show two typical examples of conventional extreme level circuits, i.e., a maximum level circuit and a minimum level circuit, respectively. The maximum level circuit, as shown in FIG. 1, includes two NPN transistors Tn1 and Tn2. Their collectors are coupled to a power supply voltage Vcc, while their emitters are coupled in common to a ground terminal through a resister R1. Two input signals V1 and V2 are applied to the bases of the two NPN transistors Tn1 and Tn2. A maximum level signal Vmax within the two input signals V1 and V2 is output from the node Vo connecting the emitters and the resistor R1. The minimum level circuit, as shown in FIG. 2, includes two PNP transistors Tp1 and Tp2. Their collectors are coupled to a ground terminal, while their emitters are coupled in common to a power supply voltage Vcc through a resister R2. Two input signals V1 and V2 are applied to the bases of the two PNP transistors Tp1 and Tp2. A minimum level signal Vmin within the two input signals V1 and V2 is output from the node Vo connecting the emitters and the resistor R2. When a plurality of inputs greater than two is provided, a corresponding number of NPN or PNP transistors are coupled in parallel with each other.
However, the maximum and minimum level circuits shown in FIGS. 1 and 2 have a drawback, as will be described below. Because of these drawbacks, when the maximum and minimum level circuits are implemented in an intermediate level circuit and a correlation detector, the circuit and the detector will suffer from defects in that cross color and/or dot disturbance occurs.
FIGS. 3 and 4 are waveform diagrams for explaining the operation of the maximum level circuit of FIG. 1 and the minimum level circuit of FIG. 2. Referring to FIGS. 3 and 4, it is assumed that a sine-wave AC input signal V2 is input to one of the input terminals, while the other input terminal is fixed at a reference potential V1. Also in the FIGS. 1 and 2, DC offset voltages between the base to emitter junctions of the transistors are neglected.
As shown in FIG. 3 for the maximum level circuit, when the input signal V2 is higher than the reference level V1, the input signal V2 is output as the output signal Vo. While the input signal V2 is lower than the reference level V2, the reference level V1 is output as the output signal Vo. However, the output signal Vo is always decreased below the input signal V2 or the reference level V1. In contrast, as shown in FIG. 4 for the minimum level circuit, when the input signal V2 is higher than the reference level V1, the the reference level V1 is output as the output signal Vo. While the input signal V2 is lower than the reference level V1, the input signal V2 is output as the output signal Vo. However, the output signal Vo is always increased above the input signal V2 or the reference level V1.
These errors of the output signal Vo are caused because the transistors are not completely cutoff if they are turned OFF and undesired saturation currents then flow therethrough. This will be described in detail below by taking the maximum level circuit of FIG. 1 as an example. The emitter coupled transistors Tn1 and Tn2 constitute a differential amplifier circuit. When the input signal V2 is equal to the reference level V1, the collector currents flowing through the transistors Tn1 and Tn2 are equal and expressed by Ie/2. The output signal VO at this time is expressed by the following Equation (1): EQU Vo=V2-VT.multidot.ln(Ie/2Is) (1)
where VT is a thermal voltage which takes 260 mV at room temperature, Ie is the collector current of the transistor Tn2, and Is is a saturation current of the transistors.
When the input signal V2 is lower than the reference level V1; that is, V2&lt;V1, with a difference of about 100 mV, the transistor Tn2 is cutoff but a collector current corresponding to the saturation current Is flows through the transistor Tn1. The collector current of the transistor Tn1 at this time is Ie. Therefore, when V2&lt;V1, EQU Vo=V1-VT.multidot.ln(Ie/Is) (2)
That is, when the input signal V2 is lower than the reference level V1 by a specified potential Va, e.g., about 100 mV or less, an error of [VT.multidot.ln 2]=18 mV is produced in the output signal Vo.
When the input signal V2 is higher than the reference level V1; that is, V2&gt;V1, with a difference of about 100 mV, the transistor Tn1 is cutoff and a collector current corresponding to the saturation current Is flows through the transistor Tn2. The collector current of the transistor Tn2 at this time is Ie. Therefore, when V2&gt;V1, EQU Vo=V2-VT.multidot.ln(Ie/Is) (3)
That is, when the input signal V2 is higher than the reference level V1 by the specified potential Va, e.g., about 100 mV or more, an error of [VT.multidot.ln2]=18 mV is also produced in the output signal Vo.
Thus, the conventional maximum level circuit has intrinsically an error of [VT.multidot.ln2].
In FIGS. 3 and 4, the waveform of the output signal Vo was rounded at the points where the input signal V2 reaches to the reference level V1. This means that the conventional circuits do not sufficiently operate as a maximum level circuit or a minimum level circuit but instead operate with the function of an adding circuit in this region. That is, when the input signal V2 is near to the reference level V1, the level of the output signal Vo is given by the ratio of the emitter resistances of the differential transistors at a low level input signal.
Because the correlation detector and the intermediate level circuit are constructed in using the conventional maximum level circuit and the minimum level circuit, the outputs of the correlation detector and the intermediate level circuit suffer from an error component of nearly 36 mV. The insufficient efficiency of the correlation detector due to the characteristics of the conventional maximum level circuit was made inconspicuous by increasing the supply voltage is make the signal amplitude large. If the signal amplitude is 1 Vpp (peak to peak voltage), as the error component is 36 mV, the relative error component ratio becomes nearly -30 dB, which has been an allowable level.
However, a more high precise maximum level circuit is demanded at present, and because the error component level has been fixed as described above, there is no means for improving its characteristics with the exception of increasing the supply voltage. Furthermore, even when realization of a low voltage maximum level circuit was demanded, a low voltage circuit could not be realized without deterioration of its characteristics.
Further, the circuits shown in FIGS. 1 and 2 have another defect in that they produce an offset of the base to emitter voltage of the transistors.